Loop structures on VHDL
As with traditional programming languages, VHDL provides a set of instructions for loop structures. Nonetheless it comes with several limitations. Due to VHDL's parallel operation, loop structures can only be used on processes
For loop
For loops are recursive structures that iterate a defined number of times before stopping. On VHDL the syntax for these loops is:
process (X)
begin
for I in 0 to 3 loop
---WHATEVER IT IS YOU WANT TO ITERATE.
end loop;
end process;
process (X)
begin
for I in 0 to 3 loop
---WHATEVER IT IS YOU WANT TO ITERATE.
end loop;
end process;