library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adder1b is port( A: in std_logic; B: in std_logic; Cin: in std_logic; Sum: out std_logic; Cout: out std_logic ); end adder1b; architecture arq_adder1b of adder1b is begin Sum <= A XOR B XOR Cin; Cout <= (A AND B)OR(A AND Cin)OR(B AND Cin); end arq_adder1b; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity aluv2 is generic(N: integer := 4); port( A: in std_logic_vector(N-1 downto 0); B: in std_logic_vector(N-1 downto 0); Cin: in std_logic; Sum: out std_logic_vector(N-1 downto 0); Cout: out std_logic; Min: out std_logic ); end aluv2; architecture arq_aluv2 of aluv2 is component subsin port( X,Y: in std_logic; O: out std_logic ); end component; signal carry: std_logic_vector(N downto 0); begin carry(0) <= NOT(Cin); GENERATOR: for I in 0 to N-1 generate ALUGEN: entity adder1b (arq_adder1b) port map(A => A(I), B => B(I), Cin => carry(I), Sum => Sum(I), Cout => carry(I+1)); end generate; Cout <= carry(N); end arq_aluv2;