---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 18:51:44 08/16/2015 -- Design Name: -- Module Name: adder1b - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adder1b is port( A: in std_logic; B: in std_logic; Cin: in std_logic; Sum: out std_logic; Cout: out std_logic ); end adder1b; architecture arq_adder1b of adder1b is begin Sum <= A XOR B XOR Cin; Cout <= (A AND B)OR(A AND Cin)OR(B AND Cin); end arq_adder1b;